1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor memory device, and more particularly, the present invention relates to a method of forming a capacitor.
This application is a counterpart of Japanese application Serial Number 039616/1997, filed Feb. 25, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 4 is a cross sectional view showing a one-bit memory cell of a conventional DRAM (Dynamic Random Access Memory), the one bit memory cell having a switching transistor, a capacitor, a bit line and a word line. The switching transistor includes a gate oxide layer 105, a gate electrode 106 and a pair of n-type impurity regions 107. The capacitor includes a storage electrode 116, 117, a dielectric layer (not shown) and a plate electrode 118, the storage electrode 116, 117 having the cylindrical structure. The bit line 111 connects to one of the n-type impurity regions 107 through a bit contact 110. The word line also serves as the gate electrode 106. The capacitor connects with the switching transistor through a storage contact 114 and a poly-silicon plug 115.
As shown in FIG. 4, the memory cell includes a p-type silicon substrate 101, an n-type guard layer 102 surrounding the memory cell, a p-type well 103 surrounded by the n-type guard layer 102, a field oxide layer 104 to separate memory cells, insulator layers 109, 112, 119, a silicon nitride layer 113 serving as a channel stopper, and a passivation layer 121.